Germanium-silicon-carbide floating gates in memories

ABSTRACT

The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide in various combinations to obtain the desired tunneling current values at the operating voltage of the memory device.

This application is a divisional of U.S. application Ser. No. 11/063,825 filed Feb. 23, 2005, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This application relates generally to semiconductor devices and device fabrication and, more particularly, to transistor gate materials and their properties, and in particular to floating gate devices.

BACKGROUND

The electronic device industry uses many different types of memory in computers and other electronic systems, such as automobiles and traffic control systems. Different types of memory have different access speeds and different cost per stored bit. For example, items of memory that require rapid recovery may be stored in fast static random access memory (RAM). Information that is likely to be retrieved a very short time after storage may be stored in less expensive dynamic random access memory (DRAM). Large blocks of information may be stored in low cost, but slow access media such as magnetic disk. Each type of memory has benefits and drawbacks, for example DRAMs lose the stored information if the power is shut off. While the magnetic memory can retain the stored information when the power is off (known as non-volatile), the time to retrieve the information is hundreds of times slower than semiconductor memory such as RAM. One type of non-volatile semiconductor memory device is electrically programmable read-only memory (EPROM). There are also electrically-erasable programmable read-only memory (EEPROM) devices. One type of EEPROM is erasable in blocks of memory at one time, and is known as flash memory. Flash memory is non-volatile like magnetic memory, is much faster than magnetic memory like RAM, and is becoming widely used for storing large amounts of data in computers. However, writing information to a conventional flash memory takes a higher write voltage than it does to write information to conventional RAM, and the erase operation in flash requires a relatively long time period.

Conventional EEPROM devices, such as flash memory, may operate by either storing electrons on an electrically isolated transistor gate, known as a floating gate, or not storing electrons on the floating gate. Typically the write (or program) operation and the erase operation are performed by another transistor gate, known as the control gate, which is located above the floating gate. A large positive voltage on the control gate will draw electrons from the substrate through the gate oxide and trap them on the floating gate. The erase operation uses a large negative voltage to drive any stored electrons on the floating gate off of the gate and back into the substrate, thus returning the floating gate to a zero state. This operation may occur through various mechanisms, such as Fowler-Nordheim (FN) tunneling. The rate at which the electrons can be transported through the insulating gate oxide to and from the floating gate is an exponential factor of both the thickness of the insulator and of the electrical height of the insulation barrier between the substrate and the floating gate. Grown gate oxides have great height, and slow tunneling.

Electronic devices have a market driven need to reduce the size and power consumption of the devices, such as by replacing unreliable mechanical memory like magnetic disks, with transistor memory like EEPROM and flash. These increasingly small and reliable memories will likely be used in products such as personal computers (PCs), personal digital assistants (PDAs), mobile telephones, laptop PCs, and even in replacing the slow hard disk drives in full sized computer systems. This is because a solid state device, such as flash memory, is faster, more reliable and has lower power consumption than a complex and delicate mechanical system such as a high speed spinning magnetic disk. What is needed is an improvement in the erase time for EEPROM devices. With improved erase times, the high density of flash memory, and a speed of operation comparable to DRAMs, flash memory might replace both magnetic memory and DRAMs in certain future computer devices and applications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a transistor with a germanium silicon carbide gate, according to embodiments of the present subject matter;

FIG. 2 illustrates a non-volatile memory element with a germanium silicon carbide gate, according to embodiments of the present subject matter;

FIG. 3 is an energy band diagram for a polysilicon gate transistor;

FIG. 4 is an energy band diagram for a silicon carbide gate transistor, according to an embodiment;

FIG. 5 is a diagram showing bandgap versus electron affinity according to an embodiment; and

FIG. 6 illustrates a diagram for an embodiment of an electronic system having devices with a floating gate transistor containing a mixture of germanium, silicon and carbon according to an embodiment.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC) structure. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to generally include n-type and p-type semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors or as semiconductors.

The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

Field effect transistors (FETs) are used in many different electronic devices, including memory devices. FETs are used both as access transistors and as memory elements. The structure of a typical FET 100 is shown in FIG. 1, where a lightly doped substrate 102 has a heavily oppositely doped source region 104 and drain region 106. The portion of the substrate 102 located between the source region 104 and the drain region 106 is known as the channel region 108, and may have a doping level that is different from the doping level of the substrate 102, and may even be counter doped to have a doping type opposite of the substrate. The substrate may be either lightly doped P type or N type, and the diffused source and drain regions will be heavily doped with the opposite doping type. There is a gate oxide 110 located over the channel region 108, and making at least some contact with each of the source region 104 and drain region 106. The gate oxide 110 is an insulator, such as thermally grown silicon dioxide, and at normal operating voltages prevents current flow from the substrate 102 to a conductive gate electrode 112. Conductive gate electrode 112 is located on top of the gate oxide 110, and also extends at least some distance over each of the source region 104 and drain region 106. Conventional gate electrodes are formed of doped polycrystalline silicon (poly or polysilicon). Embodiments of the present subject matter form gate electrode 112 with a germanium silicon carbide (GeSiC) composition. In operation, when a signal is directed to the gate 112 over an electrical connection 120, the signal voltage affects the concentration of electrical carriers in the channel region 108. For example, if a positive voltage having a greater value than what is known as the threshold voltage of the transistor 100 is applied to gate 112, then the relatively small number of electrons (negative carriers) in the P type substrate 102 will be attracted to the channel region 108 in great enough numbers to overwhelm the positive holes in the channel region, and thus temporarily convert the channel region to be N type as long as the positive voltage is applied to the gate 112. Thus a large enough positive voltage (known as the threshold voltage) on the gate 112 will electrically connect the source region 104 to the drain region 106 and turn on the transistor 100. The threshold voltage depends upon the thickness and dielectric constant of the gate insulator 110, the doping level of the channel region 108, and the electron affinity of the material forming the gate electrode 112. Thus, a gate electrode made of a material such as GeSiC may have the threshold voltage of the transistor adjusted to a desired level by changing the electron affinity of the transistor, and may thus reduce the number and size of ion implantation adjustments of the channel doping level.

The illustrative floating gate transistor 200, as shown in FIG. 2, may have a lightly doped substrate 202 with a heavily oppositely doped source region 204 and drain region 206. For example, the substrate 202 may be a lightly doped P type region, and the source region 204 and drain region 206 would then be heavily doped N+ type. The portion of the substrate 202 located between the source region 204 and the drain region 206 is again known as the channel region 208, and may have a doping level that is different from the doping level of the substrate 202. There is a gate oxide 210 located over the channel region 208, which is an insulator such as thermally grown silicon dioxide. There is an electrically floating conductive gate 212, located on top of the gate oxide 210, which unlike the previously discussed transistor 100 of FIG. 1, has no direct connection to signal voltages, and is typically called a floating gate since it is electrically floating. Conventionally, floating gates are typically formed of doped polysilicon. Embodiments of the present subject matter form floating gate 212 with a germanium silicon carbide composition. There is an inter-gate dielectric or insulator 214 which electrically separates the floating gate 212 from a control gate 216, which is also typically made of polysilicon. In operation the control gate is connected to signal voltage 220. The signal voltage 220 must be larger than the signal voltage 120 for the conventional transistor since the control gate is further from the channel region 208 and because the electrons in the channel region must be at a high enough voltage to be injected through the gate oxide 210 to become trapped on floating gate 212. A given signal voltage level will provide a current of electrons through the gate oxide 210 that depends exponentially upon the level of the signal voltage, the thickness of the gate oxide 206 and the electrical height of the barrier formed by the gate oxide 210 between the energy levels of the substrate at the channel 208 and the energy level of the floating gate 212. Changing the material of the substrate 202 or of the floating gate 212 changes the electrical height of the barrier formed by the gate oxide 210, and radically changes the amount of current that tunnels through the gate oxide 206 by means of Fowler-Nordheim tunneling. Thus, changing the tunneling barrier height results in erase operations that have larger currents at a given erase voltage level, and therefore result in faster erase times for memory devices. Another advantage of lowering the tunneling barrier height is that lower erase voltages may be used. Lower erase voltages mean lower electrical fields for a given dielectric thickness, and therefore reduced reliability issues such as time dependent dielectric breakdown of the gate insulator and inter-gate insulator.

The reason that changing the material of the substrate or of the floating gate changes the electrical height of the tunneling barrier is best understood by examination of what is known as an energy band diagram, as shown in FIG. 3 for the typical memory transistor discussed in FIG. 2 and used in flash memory. As noted above, the excellent quality of grown gate oxides results in a large electrical height of the tunneling barrier formed by the oxide. This high quality oxide results in lower programming currents and lower erase currents and causes slower memory operation. An issue with other gate insulators besides grown oxides, such as chemical vapor deposited (CVD) oxides, silicon nitride, aluminum oxide, tantalum oxide, and titanium oxides, is that the results have proven unacceptable from a device electrical performance point of view, including high levels of what are known as surface states. If the surface states are reduced by growing a thin oxide underneath the deposited oxide, then the interface between the two insulators may have large numbers of what are known as trap states, and may have band gap discontinuities and differences in the conductivity of the insulator films. Thus, changing the gate insulator to reduce the tunneling barrier height and voltage may pose problems, particularly with maintaining consistent time-dependent device electrical operation.

Another method of changing the tunneling voltage, and thus equivalently increasing the tunneling current at a particular voltage level, is to change the overall tunneling barrier height by increasing the internal energy level of the conductors on either side of the insulator, rather than by lowering the insulator barrier level. Changing the silicon substrate to some other material may cause numerous practical problems in the fabrication of devices, since so much is known about the use of silicon. Changing the material of the floating gate to a material with what is known as a lower electron affinity, denoted by the lower case Greek letter Chi (χ) results in higher tunneling currents. A lower electron affinity reduces the effective height of the insulator tunneling barrier, which as noted previously has an exponential effect on the amount of tunneling current at a given voltage.

A transistor built on a single crystal silicon substrate has a band gap diagram 300, with a conduction level 302, a valence level 304, and a Fermi level 306, as shown for a lightly doped P type silicon substrate with reference to the vacuum level 308, which represents the amount of energy it would take to remove an electron from the silicon. On the opposite side of a gate oxide 309, heavily doped N type polycrystalline silicon will have a conduction level 310, a Fermi level 312 and a valence level 314. The gate oxide 309 has an energy level value 316, whose difference from the vacuum level 308 represents the electron affinity χ of the gate oxide, typically thermally grown silicon dioxide. For good quality thermally grown silicon dioxide, the value of χ is 0.9 eV. For electrons on the floating gate conduction band 310, the value of electron affinity χ is the difference between 310 and the vacuum level 308, and for doped polysilicon is approximately 4.1 eV. Thus, the barrier that an electron tunneling from the floating gate 212 conduction band 310 to the silicon substrate 202 in the area of the channel 208, must traverse during an erase operation is the height represented by the difference between the top of the gate oxide 316 and the conduction band 310, or 4.1 eV minus 0.9 eV, or about 3.2 eV. As noted previously, the tunneling rate is an exponential factor of the height of the barrier, and the width of the oxide, which is controlled by the process parameter of gate oxide thickness.

The distance between the conduction level 310 and the valence level 314 is known as the band gap, and has a value in silicon of approximately 1.1 eV. Since the value of electron affinity for the gate oxide is not going to change, then the use of a floating gate material that has a larger band gap would result in a lower electron affinity, and thus a reduced tunneling barrier. Changing the electron affinity of the gate material also changes the threshold voltage of the transistor, and may be used in conjunction with channel doping levels and gate insulator thickness and dielectric constant to adjust the threshold voltage level.

FIG. 4 illustrates the band gap diagram 400 for an embodiment of a silicon carbide gate material. There is still a silicon substrate conduction level 402, a silicon substrate valence level 404, and a Fermi level 406 with reference to the vacuum level 408. On the opposite side of the thermally grown silicon dioxide gate oxide 409, the illustrative silicon carbide gate will have a conduction level 410, a Fermi level 412 and a valence level 414, all of which may be different from the values in the case of polysilicon gates. The gate oxide 409 still has the same energy value 416, and electron affinity χ of the gate oxide, typically 0.9 eV. The band gap for silicon carbide depends upon the ratio of silicon to carbon, and varies from the silicon value of 1.1, as noted above, to the pure carbon value of approximately 4.2 eV. For a silicon carbide mixture, the value of the band gap is about 2.1 eV to 2.6 eV depending upon the percentage of carbon. Since the conduction band is now closer to the vacuum level 408, the electron affinity is lower, about 3.7 eV, and the height of the tunneling barrier is now lower, typically below 2.8 eV, which is lower than the tunneling barrier found in the case of polysilicon of about 3.2 eV. Thus, the tunneling barrier is lowered, and even a small difference in tunneling barrier height causes a large change in tunneling current. For germanium carbide, a very similar band diagram shows a tunneling barrier that extends from a larger value than that of polysilicon for a pure germanium gate of 3.6 eV, to a barrier value that is the same as the polysilicon value of 3.2 eV at a 4% carbon content, to lower values for increased carbon content above the 4% level. The values for silicon, silicon carbide and germanium carbide are discussed in more detail with respect to FIG. 5 later in this disclosure. Increased tunneling current flow at a given erase voltage value results in much faster erase operations and improved EEPROM or flash memory operational speeds.

Crystalline silicon carbide and silicon germanium carbide can be epitaxially grown on a silicon substrate and may be used in both metal oxide semiconductor field effect transistors (MOSFET) or bipolar transistor devices, with the silicon substrate acting as a seed layer for crystal growth. In an embodiment the silicon carbide, germanium carbide and silicon germanium carbide are microcrystalline or amorphous. Such microcrystalline layers or amorphous layers may be grown on insulator layers such as silicon dioxide gate insulator layers, or other insulator layers, by chemical vapor deposition (CVD), laser assisted CVD, plasma CVD, ultra-high vacuum CVD, or sputtering.

FIG. 5 is a graph 500 that illustrates the ability to adjust the tunneling barrier height, and thus the tunneling barrier current level, for various embodiments of mixtures of silicon 504, germanium 506, and carbon in the form of diamond 508. The values of germanium carbide of varying percentages of germanium are shown by the line connecting 506 and 508, including the interesting point 510 where a 4% carbon value in germanium provides the same band gap 1.1 eV as pure silicon 504, but with a lower electron affinity χ and thus improved tunneling currents and faster erase operations without other significant electrical changes in the transistor operation due to changes in the band gap value. Silicon carbide values are projected on the line from 504 to 508, with silicon carbide having a band gap with a 2.1 eV value shown at 512. Various embodiments of the present disclosed methods and devices can be found in the region of the graph between 510 and 512 and the entire area between the lines representing germanium carbide and silicon carbide compositions. An illustrative silicon germanium carbide material with equal amounts of silicon and germanium and varying amounts of carbon would have a band gap to electron affinity χ curve that fits about halfway between the germanium carbide line and the silicon carbide line.

FIG. 6 depicts a diagram of an embodiment of a system 600 having a controller 602 and a memory 606. Controller 602 and/or memory 606 include a transistor having a gate electrode made of a mixture of germanium, silicon and carbon. System 600 also includes an electronic apparatus 608, and a bus 604, where bus 604 may provide electrical conductivity and data transmission between controller 602 and electronic apparatus 608, and between controller 602 and memory 606. Bus 604 may include an address, a data bus, and a control bus, each independently configured. Bus 604 also uses common conductive lines for providing address, data, and/or control, the use of which may be regulated by controller 602. In an embodiment, electronic apparatus 608 includes additional memory devices configured similarly to memory 606. Electronic apparatus 608 may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers. An embodiment includes an additional peripheral device or devices 610 coupled to bus 604. In an embodiment controller 602 is a processor. Any of controller 602, memory 606, bus 604, electronic apparatus 608, and peripheral device or devices 610 may include a gate electrode formed of a mixture of silicon, germanium and carbon in accordance with the disclosed embodiments.

System 600 may include, but is not limited to, information handling devices, telecommunication systems, and computers. Peripheral devices 610 may include displays, additional storage memory, or other control devices that may operate in conjunction with controller 602 and/or memory 606. It will be understood that embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to a particular type of memory device.

CONCLUSION

An embodiment has a floating gate transistor with a gate made of a material having a lower tunneling barrier and thus lower erase times. Another embodiment has the floating gate formed of germanium silicon carbide. Another embodiment has the composition of the floating gate determined by a desired tunneling current. Another embodiment includes a transistor with a conventional gate having the composition of the germanium silicon carbide adjusted to optimize the threshold of a metal oxide semiconductor field effect transistor (MOSFET).

An embodiment for a method for forming a floating gate memory device includes forming a floating gate having a lower tunneling barrier by forming the gate of a mixture of germanium, silicon and carbon. Another embodiment includes a method of storing data by setting the voltage of the control gate, drain diffusion and source diffusion to either trap electrons on a floating gate made of germanium, silicon and carbon, or by ejecting trapped electrons from the floating gate by Fowler-Nordheim tunneling.

Applications include structures for transistors, memory devices such as flash, and electronic systems with gates containing a mixture of germanium, silicon and carbon, and methods for forming such structures.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description. The scope of the embodiments of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. 

1. A method of forming a memory cell, comprising: forming a source region, a drain region, and a channel region disposed between and separating the source and drain regions, in a semiconductor substrate; forming a gate oxide layer on and contacting the semiconductor substrate over at least the channel region and over at least portions of the source and drain regions; forming an electrically isolated floating gate on and contacting the gate oxide layer over the channel region and over at least portions of each of the source and drain regions, the floating gate formed of a mixture consisting essentially of silicon, germanium and carbon, the arrangement of the floating gate and the gate oxide layer forming a tunnel barrier having a tunneling barrier height; selecting a value for the tunneling barrier height to match an operational parameter of the channel region such that selecting the value selects an electron affinity for the mixture; controlling an amount of the carbon in the mixture to match the selected electron affinity for the floating gate; forming an inter-gate insulator over the floating gate; and forming a control gate over the inter-gate insulator and separated from the floating gate by the inter-gate insulator.
 2. The method of forming a memory cell of claim 1, wherein the mixture of germanium, silicon and carbon is selected to provide a lower electron affinity than a floating gate formed of doped polycrystalline silicon.
 3. The method of forming a memory cell of claim 1, wherein the floating gate is micro-crystalline or amorphous.
 4. The method of forming a memory cell of claim 1, wherein the floating gate is conductive.
 5. A method of forming a field effect transistor, comprising: forming at least one source diffusion region having a first doping type in a semiconductor substrate having a second doping type opposite from the first doping type; forming at least one drain diffusion region having the first doping type in the semiconductor substrate at a location separated from the at least one source diffusion by a desired distance to form a channel region between one source and one drain diffusion regions; forming a gate insulator layer on and contacting the channel region, the gate insulator layer having a first thickness on the substrate and extending over the entire channel region and at least a portion of one source diffusion region and at least a portion of one drain diffusion regions; forming a floating gate electrode on and contacting the gate insulator layer, the floating gate electrode formed over the gate insulator extending over at least a portion of the one source and one drain diffusion regions, the floating gate electrode formed of a first percentage of germanium atoms, a second percentage of silicon atoms, and a third percentage of carbon atoms, the arrangement of the floating gate electrode and the gate insulator layer forming a tunnel barrier having a tunneling barrier height; selecting a value for the tunneling barrier height to match an operational parameter of the channel region such that selecting the value selects an electron affinity for the floating gate electrode; controlling the third percentage of carbon atoms to match the selected electron affinity for the floating gate electrode; forming an inter-gate insulator over the floating gate electrode; and forming a control gate over the inter-gate insulator.
 6. The method of claim 5, wherein forming the floating gate electrode includes setting the first percentage of germanium to about 96%, setting the second percentage of silicon to about 0%, and setting the third percentage of carbon to about 4%, forming germanium carbide having a band gap of about 1.1 eV, and an electron affinity of about 3.8 eV.
 7. The method of claim 5, wherein forming the floating gate electrode includes setting the first percentage of germanium to about 25%, setting the second percentage of silicon to about 25%, and setting the third percentage of carbon to about 50%, forming germanium silicon carbide having a band gap of about 2.5 eV, and an electron affinity of about 2.9 eV.
 8. The method of claim 5, wherein forming the floating gate electrode includes setting the percentages of germanium, silicon and carbon to form germanium-silicon carbide having a band gap greater than 1.1 eV, and an electron affinity of less than 4 eV.
 9. The method of claim 5, wherein forming the floating gate electrode includes setting the first, second and third percentages to obtain a desired tunneling current through the first thickness of the gate insulator at a preselected voltage level.
 10. The method of claim 5, wherein the semiconductor substrate includes silicon and forming the gate insulator includes thermally growing silicon dioxide at an elevated temperature in an oxidizing ambient, and wherein the floating gate is formed with no direct electrical connection to the semiconductor substrate or to the control gate.
 11. A method of forming a nonvolatile memory cell, comprising: forming a source region separated from a drain region by a channel region in a semiconductor substrate; forming a gate oxide layer on and contacting the semiconductor substrate; forming a floating gate on and contacting the gate oxide layer and over the channel region of silicon, germanium and carbon, the arrangement of the floating gate and the gate oxide layer forming a tunnel barrier having a tunneling barrier height; selecting a value for the tunneling barrier height to match an operational parameter of the channel region such that selecting the value selects an electron affinity for the floating gate; controlling an amount of the carbon in the floating gate to match the selected electron affinity for the floating gate; forming an inter-gate insulator over the floating gate; and forming a control gate over the inter-gate insulator and separated from the floating gate by the inter-gate insulator.
 12. The method of claim 11, wherein a mixture of germanium, silicon and carbon is selected to provide an electron affinity of less than 4 eV.
 13. The method of claim 11, wherein forming the floating gate includes a conductive and amorphous combination of germanium, silicon and carbon.
 14. The method of claim 11, wherein forming the floating gate includes setting a percentage of each of the silicon, germanium and carbon to obtain a desired tunneling current through the gate insulator at an operating voltage level.
 15. The method of claim 11, wherein forming the floating gate includes setting a percentage of each of the silicon, germanium and carbon to obtain a desired conduction band value different from a conduction band value of the semiconductor substrate.
 16. The method of claim 11, wherein forming the floating gate includes setting a percentage of each of the silicon, germanium and carbon to obtain a desired conduction band value that is at least 1.0 eV higher than a conduction band value of the semiconductor substrate.
 17. The method of claim 11, wherein forming the nonvolatile memory cell includes silicon for the semiconductor substrate.
 18. The method of claim 15, wherein forming the nonvolatile memory cell includes thermally growing silicon dioxide on the semiconductor substrate at a elevated temperature in an oxidizing ambient to form silicon dioxide.
 19. The method of claim 11, wherein forming the nonvolatile memory cell includes forming the floating gate with no direct electrical connection to the semiconductor substrate or to the control gate.
 20. The method of claim 11, wherein forming the nonvolatile memory cell includes forming the floating gate of a mixture of germanium, silicon and carbon having at least enough electrical conductivity to redistribute trapped electrons essentially evenly throughout the film during a single clock cycle.
 21. The method of claim 20, wherein forming the nonvolatile memory cell includes doping the floating gate to increase electrical conductivity.
 22. A method of forming a memory device, comprising: forming an array of memory cells, each comprising a source region, separated from a drain region by a semiconductive channel region; forming an insulator on and contacting the semiconductive channel region; forming a gate of germanium, silicon and carbon on and contacting the insulator adjacent the semiconductive channel region, the arrangement of the gate and the insulator forming a tunnel barrier having a tunneling barrier height; selecting a value for the tunneling barrier height to match an operational parameter of the semiconductive channel region such that selecting the value selects an electron affinity for the gate; controlling an amount of the carbon in the gate to match the selected electron affinity for the gate; forming an intergate insulator on the gate; forming a control gate on the intergate insulator adjacent the gate; coupling the control gate to a word line; coupling the array of memory cells to addressing circuitry; and coupling the array of memory cells to control circuitry.
 23. The method of claim 22, wherein forming the gate includes selecting percentages of germanium, silicon and carbon to obtain a desired current flow through the first insulator at an operating condition.
 24. The method of claim 23, wherein forming the gate includes about half germanium carbide and about half silicon carbide, having a band gap of about 2.5 eV and an electron affinity of about 3 eV.
 25. The method of claim 22, wherein the source region, the drain region and the semiconductive channel region are portions of a doped silicon substrate having a first doping type, and the source and drain regions are formed by counter doping the silicon substrate with a larger doping level of a second type.
 26. The method of claim 25, wherein forming the insulator includes thermally growing silicon dioxide on the silicon substrate.
 27. The method of claim 22, wherein forming the gate includes providing electrical isolation of the gate from electrical signals from the substrate and control gate, wherein the electrical isolation is sufficient to provide long term unpowered storage of electrons.
 28. A method comprising: providing a controller; and coupling an integrated circuit to the controller, wherein the integrated circuit includes at least one transistor having a channel region, a floating gate, and a control gate, wherein the floating gate includes carbon and at least one of germanium and silicon, and has a lower electron tunneling barrier for the floating gate than a doped polycrystalline silicon floating gate, the floating gate formed by selecting a value for the electron tunneling barrier to match an operational parameter of the channel region such that selecting the value selects an electron affinity for the floating gate and by controlling an amount of the carbon in the floating gate to match the selected electron affinity for the floating gate.
 29. The method of claim 28, wherein coupling an integrated circuit to the controller includes coupling a non-volatile memory device formed as the integrated circuit.
 30. The method of claim 28, wherein providing a controller includes providing a processor.
 31. The method of claim 28, wherein coupling an integrated circuit to the controller includes coupling a mixed signal integrated circuit formed as the integrated circuit having the dielectric layer contacting the conductive layer.
 32. The method of claim 28, wherein the method is a method of forming an information handling system.
 33. The method of claim 1, wherein the method includes controlling the amount of the carbon in the mixture to match a selected threshold voltage.
 34. The method of claim 1, wherein the method includes doping the channel region based on the amount of carbon in the mixture. 